FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel Inverter

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This paper proposes a new Asymmetrical multilevel inverter topology with
reduced number of switches. This topology is superior to the existing
multilevel inverter (MLI) configurations in terms of lower total harmonic
distortion (THD) value and lower cost. The idea incorporates a new module
setup comprising of four different voltage sources having voltage output
levels in a specific ratio. The proposed topology uses a novel pulse width
modulation (PWM) technique (as presented) to control the gating pulses. The
operation is simulated using MATLAB/SIMULINK and its results are
validated through FPGA Spartan 3 based hardware prototype inverter (using
three voltage sources to produce a 7 level output, which may be extended to
15 level). The circuit complexity is drastically reduced and it is suitable for
medium and high power applications. THD for the output is quite low when
compared with the conventional inverter

Paper's Information

Publisher International Journal of Power Electronics and Drive System (IJPEDS)
Index at 04 January 2017 13:44 p.m.
Source Type Journal
Source Title International Journal of Power Electronics and Drive Systems (IJPEDS) 340~348 pages. Vol. 7 Number.2
Cited 2 times
Keywords Field programmable gate array, Multilevel inverter, Pulse width modulation, Reduced switch MLI, total harmonic distortion,


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