FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel Inverter

Author :

Download Paper

Abstract

This paper proposes a new Asymmetrical multilevel inverter topology with
reduced number of switches. This topology is superior to the existing
multilevel inverter (MLI) configurations in terms of lower total harmonic
distortion (THD) value and lower cost. The idea incorporates a new module
setup comprising of four different voltage sources having voltage output
levels in a specific ratio. The proposed topology uses a novel pulse width
modulation (PWM) technique (as presented) to control the gating pulses. The
operation is simulated using MATLAB/SIMULINK and its results are
validated through FPGA Spartan 3 based hardware prototype inverter (using
three voltage sources to produce a 7 level output, which may be extended to
15 level). The circuit complexity is drastically reduced and it is suitable for
medium and high power applications. THD for the output is quite low when
compared with the conventional inverter


Paper's Information

Publisher International Journal of Power Electronics and Drive System (IJPEDS)
Index at 04 January 2017 13:44 p.m.
Source Type Journal
Source Title International Journal of Power Electronics and Drive Systems (IJPEDS) 340~348 pages. Vol. 7 Number.2
Cited 2 times
Keywords Field programmable gate array, Multilevel inverter, Pulse width modulation, Reduced switch MLI, total harmonic distortion,

References


  1. Nabae; I. Takahashi; H. Akagi
    A new neutral-point-clamped PWM inverter
    Post on 1981
  2. C. Bharatiraja, R. Latha, Dr. S. Jeevananthan, S. Raghu and Dr. S.S. Dash
    Design And Validation Of Simple Space Vector PWM Scheme For Three-Level NPC - MLI With Investigation Of Dc Link Imbalance Using FPGA IP Core
    Post on 2013
  3. Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng
    Multilevel inverters: a survey of topologies, controls, and applications
    Post on None
  4. P. Jamuna; Dr. C. Christober Asir Rajan
    New Asymmetrical Multilevel Inverter Based Dynamic Voltage Restorer
    Post on 2013
  5. Nikhil; V.K.; Joseph, K.D
    A Reduced Switch Multilevel Inverter for Harmonic Reduction
    Post on 2012
  6. Al-Judi; A.; Bierk, H.; Nowicki, E
    A modified cascaded multilevel inverter with reduced switch count employing bypass diodes
    Post on 2009
  7. Ebrahim B., Mohammad F., Farshid N
    Symmetric and asymmetric multilevel inverter topologies with reduced switching devices
    Post on 2012
  8. E. Babaei
    A cascade multilevel inverter topology with reduced number of switches
    Post on 2008
  9. M. Calais, V.G. Agelidis
    Multilevel converters for single-phase grid connected photovoltaic systems-an overview
    Post on 1998
  10. S.B. Kjaer; J.K. Pedersen; F. Blaabjerg
    A review of single-phase grid connected inverters for photovoltaic modules
    Post on 2005
  11. P.K. Hinga; T.; Ohnishi; T. Suzuki
    A new PWM inverter for photovoltaic Power generation system
    Post on 1994
  12. Boost, M.A.; Ziogas, P.D
    State-of-the-art carrier PWM techniques: a critical evaluation
    Post on 1998
  13. J. Rodríguez; J. S. Lai; F. Z. Peng
    Multilevel inverters: A survey of topologies, controls, and applications
    Post on 2002
  14. Bharatiraja, C., Raghu, S., Rao, P., Paliniamy, K.R.S
    Comparative analysis of different PWM techniques to reduce the common mode voltage in three-level neutral-point- clamped inverters for variable speed induction drives
    Post on 2013
  15. Alishah, R.S., Hosseini, S.H
    A new multilevel inverter structure for high-power applications using multi-carrier PWM switching strategy
    Post on 2015
  16. Gnana Prakash, M., Balamurugan, M, Umashankar, S
    A new multilevel inverter with reduced number of switches
    Post on 2014
  17. Hemanthakumar, R., Raghavendrarajan, V., AjinSekhar, C.S., Sasikumar, M
    A novel hybrid negative half cycle biased modulation scheme for cascaded multilevel inverter
    Post on 2014